(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of determining when the endpoint of a copper Chemical Mechanical Polishing process has been reached.
(2) Description of the Prior Art
One major aspect of creating semiconductor devices is the aspect of creating surfaces of near ideal planarity or flatness. This requires polishing of semiconductor surfaces with the objective of removing unwanted particles from the surface.
It is well known in the art that forming semiconductor devices requires a large number of complex interrelated processing steps to form particular device features, these processing steps typically use and depend on a flat surface. The creation of semiconductor devices further frequently requires the creation of these devices in a number of overlaying layers of material, which further complicates the required processing steps since planarity must be maintained from layer to layer within the device structure. Good surface planarity is critically important to lithography processes since these processes depend on maintaining depth of focus. Two common techniques used to achieve planarity on a semiconductor surface are a Spin-On-Glass (SOG) etchback process and a Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the surface of the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The motion of the wafer relative to the polishing pad creates abrasive action. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals which comprise an insulating layer of the wafer, while the size of the silicon dioxide particles controls the physical abrasion of the surface of the wafer. The polishing of the wafer is accomplished when the silicon dioxide particles abrade away the oxidized chemicals. An important parameter during the polishing operation is the polishing efficiency, which is the amount of material that is removed from the surface of the substrate by the CMP process as a function of time. This efficiency is, among others, dependent on the density of the pattern or the concentration of the raised areas on the surface that is being polished.
During the CMP process, the allocated polishing time and the downforce exerted on a wafer that is being polished are typically fixed and independent of the topography of the surface that is being polished. The removal rate of material from a wafer has been shown to be directly proportional to the downward force exerted on the surface that is being polished and inversely proportional to the surface area that comes into contact with the polishing pad. The removal rate of material therefore increases as the size of the polished surface decreases, and visa versa. Since different integrated circuits have different surface topographies, the material removed during a CMP process may vary from substrate to substrate and between various layers within a device structure.
Because dimensions of Integrated Circuit (IC) devices in advanced IC""s continue to decrease, the dimensions of conductors and interconnection elements, which connect and interconnect those integrated circuit devices, also continue to decrease. Dimensions of conductor and interconnection elements, which directly contact IC devices, have typically decreased the greatest, thus becoming the smallest in dimension of conductor and interconnecting elements in advanced IC""s. These narrow conductors and interconnections typically comprise the first conductor or interconnection level, which contacts an integrated circuit device. First conductor levels have traditionally been formed from aluminum metal or aluminum metal alloys. First interconnection levels (i.e. first conductive contact studs) are typically formed using tungsten. Conducting lines in the era of micron and sub-micron device features must have a high level of conductivity while simultaneously showing limited susceptibility to degradative phenomenon such as electromigration, a requirement that grows in importance as wire widths decrease. Electromigration may, under extremely high current densities, result in an electrical open and is most common in aluminum metal and aluminum metal alloy conductor and interconnect elements and has not typically been observed in interconnects made of tungsten. Although copper and copper alloys possess the high electrical conductivity and low electromigration susceptibility desired for conductor elements and interconnection elements within advanced IC""s, methods through which copper and copper metal alloys may be formed into conductor and interconnection elements within advanced IC""s are neither well developed nor well understood.
Thus, in this regard, aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than other better conductors such as copper, gold, and silver. Copper does provide the advantages of improved conductivity and reliability, but does as yet provide a challenge where a layer of copper must be etched using conventional methods of photolithography and reactive ion etching (RIE). This is due to the fact that copper does not readily form volatile species during the process of RIE. To circumvent these problems, other methods of creating interconnect lines using copper have been proposed such as depositing the copper patterns using methods of Chemical Vapor Deposition (CVD) or selective electroless plating. The composition of the deposited layer of metal, if the preferred element contained in the layer of metal is copper, can be changed by the addition of other metallic substances in order to improve deposition results. Copper has only recently gained more attention as an interconnect metal. Copper is known for its relatively low cost and low resistivity, copper however also has a relatively large diffusion coefficient into surrounding dielectrics such as silicon dioxide and silicon. Copper has the additional disadvantage of being readily oxidized at relatively low temperatures, therefore conventional photoresist processing cannot be used because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment. Copper from an electrical interconnect may diffuse into a surrounding layer of dielectric (such as a layer of silicon dioxide), causing the dielectric to become conductive while at the same time decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier layer in order to prevent diffusion into the surrounding silicon dioxide layer. Silicon nitride can serve as a diffusion barrier to copper, but prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and the substrate. Copper further has low adhesive strength to various insulating layers, and it is inherently difficult to mask and etch a blanket copper layer into intricate circuit structures. Copper is also more resistant than aluminum to electromigration, a quality that grows in importance as wire width decreases.
In a typical CMP process, material is removed from the surface of a microelectronic substrate, the wafer is pressed against a planarizing medium (a polishing pad), an abrasive planarizing fluid or slurry is distributed over the surface that is being polished. The process of polishing or planarization is performed under controlled conditions of chemical environment (abrasive action of the slurry, controlled by the size and abrasive characteristics of the abrasive particles contained in the slurry providing etch and/or oxidation of the surface that is being polished), relative rotational velocity of polishing pad with respect to the (rotating) surface that is being polished, pressure applied to the polishing pad at the time of contact with the surface that is being polished, and temperature of the polishing media.
FIG. 1 shows a Prior Art CMP apparatus. A polishing pad 20 is attached to a circular polishing table 22 which rotates in a direction indicated by arrow 24 at a rate in the order of 1 to 100 RPM. A wafer carrier 26 is used to hold wafer 18 face down against the polishing pad 20. The wafer 18 is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer carrier 26 also rotates as indicated by arrow 32, usually in the same direction as the polishing table 22, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table 22, the wafer traverses a circular polishing path over the polishing pad 20. A force 28 is also applied in the downward vertical direction against wafer 18 and presses the wafer 18 against the polishing pad 20 as it is being polished. The force 28 is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft 30 that is attached to the back of wafer carrier 26. Slurry 21 is provided to the top of the polishing pad 20 to further enhance the polishing action of polishing pad 20.
Critical to the polishing operation is to remove, in a cost effective manner, the excess material from the surface that is being polished while maintaining or creating ideal planarity of this surface. While many of the parameters that control the polishing process are aimed at increasing the rate at which excess particles are removed from the surface, equally important is it to have and employ methods that control the end of the polishing process. Under-polishing results in unwanted material remaining in place on the polished surface, creating problems of planarity or problems of functionality or reliability of the devices that are being created. Over-polishing can have equally severe impact on the surface that is being polished and with that on the device that is being created. Conventional methods of controlling the period during which the polishing process is applied depend on estimating the time required to achieve the expected results. This method has serious problems of the accuracy of the estimates, a fact that can readily be appreciated with the realization of the numerous parameters that impact a polishing process such as slurry effectiveness (abrasive action and the thereon dependent particle removal rate), environmental temperature, hardness and condition of the surface that is being polished at the time of initiation of the polishing action, pattern density on or status of the surface that is being polished, precise control of applied pressure and relative rotational speeds of the rotating surfaces, status and wear of the polishing pad, and the like. For these and other reasons, it is desirable to have a method that monitors actual conditions that exist on the surface that is being polished and that do not depend, to the maximum extent possible, on environmental impact and parameters. Another conventional method to determine polishing end point is to actually remove the wafer from the polishing apparatus and measure the thickness of the wafer at the time that the wafer is removed from the polishing apparatus. It is easy to grasp that this method is extremely intrusive on a manufacturing process in addition to being time consuming and of debatable accuracy (when is the real end point reached, how often does this process need to be repeated and at what intervals, what if the end point is almost reached, etc.). Yet another method intermittently measures exposed surfaces of the wafer and follows the progress of surface removal in this manner. This method too is cumbersome and open to numerous ways of measuring erroneous data that are, in addition, difficult to correlate with operational parameters or with actual conditions as they exist on non-observed portions of the surface that is being polished.
For all of these factors, it is required to provide a method of CMP end point detection that is not time consuming, simple, dependable (repeatable) and non-intrusive. Above all, the method must be cost effective if the method is to be applied to a significant extent in today""s highly competitive semiconductor manufacturing environment.
U.S. Pat. No. 5,949,927 (Tang) shows a CMP endpoint process where the laser reflects off the wafer, not the pad, and measures slurry chemical content.
U.S. Pat. No. 5,722,875 (Iwahita et al.) shows a CMP endpoint for Cu using the temperature of the pad.
U.S. Pat. No. 5,483,568 (Yano et al.) measure CMP endpoint by density of slurry particles in the slurry.
U.S. Pat. No. 6,015,333 (Obeng) shows CMP endpoint method by measuring the luminescence in the waste slurry.
U.S. Pat. No. 6,066,564 (Li et al.) shows an endpoint process by measuring the byproduct of a CMP.
U.S. Pat. No. 5,705,435 Chen), U.S. Pat. No. 6,075,606 (Doan), and U.S. Pat. No. 5,685,766 (Mattingly et al.) teach other CMP endpoint processes.
A principle objective of the invention is to provide a method to accurately measure the status of a copper Chemical Mechanical Polishing operation.
Another objective of the invention is to provide a method for copper CMP that does not depend on or require an observation window to monitor polishing status, reducing the cost of the polishing operation.
Yet another objective of the invention is to provide a method that monitors the polishing of a copper surface and that provides a continuous indication of the status of the polishing action.
A still further objective of the invention is to provide a method of monitoring the polishing of a copper surface that is independent of the characteristics or nature of the surface that is being polished, such as density of pattern and density of the copper on the surface that is being polished.
In accordance with the objectives of the invention a new method is provided for endpoint detection of the polishing of a copper surface. The amount of copper dioxide that is removed from a surface that is being polished is monitored by means of a laser beam that is reflected off the polishing pad that is used for the polishing operation. The reflected light beam is analyzed for color content, based on this analysis it can be determined at what time no more copper dioxide is present on the surface of the polishing pad. This is the time that the process of removing copper from the surface that is being polished is complete and the polishing process can be terminated.